Real-time systems are often used to control and monitor other systems such as chemical processes, aircraft flight controls, spacecraft, and automobile engines. A real-time system is characterized by the requirement that the system complete some or all of its tasks before the occurrence of an external event which occurs at a fixed time. Often the tasks and the external events are periodic. The implication of this is that the processing performed by the system must be fast, and more importantly, predictable in duration. Significant variations in the amount of time required to perform a task, from one invocation to another, are not acceptable.
It is becoming increasingly common to build real-time systems using a distributed architecture. In a distributed system, the processing is divided between more than one hardware processor. The processors are interconnected by a communications bus, or network, to provide sharing of data and cooperation between the processors. Often, the communications across the bus is one of the slowest parts of the processing. Variations in the timing of the communication are most likely to impact the overall response time. One source of delay is when a first processor is busy when a second processor needs to communicate with it. The second processor will be stalled until the first processor becomes available.
One solution is to provide a secondary device, a communications interface, associated with the processor, which is dedicated to handling the communications. It will accept data from the communications bus and make it available to the processor, and accept data from the processor and transmit it over the bus. Often, the mechanism used to transfer data between the processor and the communications interface becomes the bottleneck. This transfer mechanism is a shared resource which can only be used by one of the processor or the communications interface at a time. If it is in use by the processor, the communications interface can not operate, and the communications over the bus is again stalled.
In some applications, such as spacecraft system, electrical power is in limited supply. One method used to conserve this resource is to power down hardware which is not in use, such as the distributed processors. However, it would be desirable that communications with the device still be available while the processor is powered down.
In some implementations, the processor and the communications interface are built into the same integrated circuit chip. However, the capability may be provided to disable the processor portion of the chip and couple the chip to an external processor. The communications interface needs to operate normally, transferring data to and from the external processor.
There is a need for a bi-directional data transfer mechanism between a processor and a communications interface. The transfer mechanism must give first priority to the communications interface; it must work with the processor powered down, allowing the communications interface to function; and, in a single chip implementation, it must also work with an external processor when the internal processor is disabled.